Due to the constant increase in the number of transistors in each integrated circuit (IC), the surface area of each chip is increased. Accordingly, the delay time of each signal is prolonged, and the power consumption is increased. To effectively resolve this problem, a three-dimensional IC (3DIC) stacking technique is being developed for reducing the delay time of each signal and decreasing the power consumption. In the 3DIC stacking technique, multiple ICs are vertically stacked, and through silicon vias (TSVs) running through silicon substrates are formed for transmitting signals and supply voltages between different ICs, so that the size of the chip is effectively reduced.
The 3DIC stacking technique has three major steps. The first step is to form TSV channels and fill in a conductive metal, the second step is wafer thinning, and the third step is chip stacking and integration. In the first step, due to the limitation of existing fabrication techniques, the thin insulating film (for example, SiO2) serving as the sidewall of a TSV may be broken or contaminated with impurities during the fabrication process, and as a result, an open circuit of the TSV or a short circuit of the silicon substrate may be caused. Besides, in the third step, when multiple ICs are stacked and integrated, the TSV may be improperly connected and open-circuited (i.e., the TSV cannot provide a valid path for transmitting signals among different ICs) due to a small offset of the ICs.
In the conventional design of a 2DIC, multiple paths are formed for transmitting a same signal at the same time, so as to make sure that data is correctly transmitted. However, in the 3DIC stacking technique, if a TSV and the silicon substrate are short-circuited, the leakage current produced by the supply voltage will enter the silicon substrate through the TSV, and accordingly the voltage level of the entire silicon substrate will drift and become unstable. As a result, signals transmitted in other TSVs may not be correctly transmitted due to the drifted voltage level of the silicon substrate. Thereby, many manufacturers in the 3DIC field are trying to develop a data transmission path circuit which can automatically detect any TSV short circuit and comes with a data self-repair function.